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19-4504; Rev 0; 9/09
1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP
General Description
The MAX8649 high-efficiency DC-to-DC step-down switching regulator delivers up to 1.8A of output current. The device operates from a 2.5V to 5.5V input voltage range, making it future proof for next-generation battery technologies. The output voltage is I2C programmable from 0.75V to 1.38V. Fully differential remote sense ensures precise DC regulation at the load. Total output error is less than 2% over load, line, and temperature. The MAX8649 operates at a 3.25MHz fixed frequency. The high operating frequency minimizes the size of external components. The switching frequency of the converter can be synchronized to the master clock of the application. When synchronizing to an external clock, the MAX8649 measures the frequency of the external clock to ensure that the clock is stable before changing the switching frequency to the external clock frequency. An on-board DAC allows adjustment of the output voltage in 10mV steps. The output voltage can be programmed directly through the I 2 C interface, or by preloading a set of on-board registers and using the two VID logic signals to select the appropriate register. Other features include internal soft-start control circuitry to reduce inrush current, output overvoltage, overcurrent, and overtemperature protection.
Features
o 1.8A Guaranteed Output Current o I2C Programmable VOUT (750mV to 1.38V in 10mV Steps) o o o o Operates from 2.5V to 5.5V Input Supply On-Chip FET and Synchronous Rectifier Fixed 3.25MHz PWM Switching Frequency Synchronizes to 13MHz, 19.2MHz, or 26MHz System Clock when Available o Small 1.0H Inductor o Initial Accuracy 0.5% at 1.25V Output o 2% Output Accuracy Over Load, Line, and Temperature o o o o Power-Save Mode Increases Light Load Efficiency Overvoltage and Overcurrent Protection Thermal Shutdown Protection 400kHz I2C Interface
MAX8649
o < 1A Shutdown Current o 16-Bump, 2mm x 2mm WLP Package
Ordering Information
PART MAX8649EWE+T TEMP RANGE -40C to +85C PIN-PACKAGE 16 Bump WLP (0.5mm pitch)
Applications
Cell Phones and Smartphones PDAs and MP3 Players
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration
TOP VIEW (BUMPS ON BOTTOM
Typical Operating Circuit
0V TO 4.0V 2.5V TO 5.5V
+
IN1 A1 SNS+ B1 SNSC1 VDD D1
AGND A2 EN B2 VID0 C2 SDA D2
VID1 A3 LX B3 PGND C3 SCL D3
IN2 A4
MAX8649
VDD 0.1F
IN2 10F 1H LX 10F 0.1F 0.1F VOUT (0.75V TO 1.38V)
LX B4 PGND
2.5V TO 5.5V 11 2.2F 0.1F
SCL SDA IN1 FSYNC EN VID0 VID1 AGND
PGND
C4 SYNC D4
SNS+ CPU SNS-
WLP 0.5mm PITCH
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
ABSOLUTE MAXIMUM RATINGS
IN1, IN2 to AGND ..................................................-0.3V to +6.0V VDD to AGND.........................................................-0.3V to +4.0V LX, SNS+, VID0, VID1, EN to AGND..........-0.3V to (VIN1 + 0.3V) SCL, SDA, SYNC to AGND.........................-0.3V to (VDD + 0.3V) PGND, SNS- to AGND...........................................-0.3V to +0.3V RMS LX Current ..............................................................1800mA Continuous Power Dissipation (TA = +70C) 16-Bump WLP 0.5mm Pitch (derate 13mW/C above +70C) ............................1040mW Operating Temperature Range ...........................-40C to +85C Junction to Ambient Thermal Resistance (JA) (Note 1)..76C/W Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Bump Temperature (soldering, reflow) ............................+260C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VDD = 1.8V, TA= -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER IN1, IN2 Operating Range VDD Operating Range VDD Undervoltage Lockout (UVLO) Threshold VDD UVLO Hysteresis IN_ Undervoltage Lockout (UVLO) Threshold IN_ UVLO Hysteresis VDD Shutdown Supply Current IN1, IN2 Shutdown Supply Current IN1, IN2 Standby Supply Current VIN1 = VIN2 = 5.5V, EN = VDD = AGND VIN1 = VIN2 = 5.5V, EN = VDD = AGND VIN1 = VIN2 = 5.5V, SCL = SDA = VDD, EN = AGND, I2C ready VIN1 = VIN2 = VDD = 3.6V, SCL = SDA = VDD, EN = AGND, I2C ready TA = +25C TA = +85C TA = +25C TA = +85C TA = +25C TA = +85C TA = +25C TA = +85C EN, VID0, VID1 SYNC, SCL, SDA EN, VID0, VID1 SYNC, SCL, SDA TA = +25C TA = +85C -1 0.01 0.01 1.4 0.7 x VDD 0.4 0.3 x VDD +1 VIN falling 2.10 VDD falling CONDITIONS MIN 2.5 1.8 0.54 0.865 50 2.15 70 0.01 0.01 0.25 0.25 0.35 0.35 0.02 0.02 1 A 1 1 1 2.20 TYP MAX 5.5 3.6 1.35 UNITS V V V mV V mV A A A
VDD Standby Supply Current LOGIC INTERFACE Logic Input High Voltage (VIH) Logic Input Low Voltage (VIL) SDA, SCL, SYNC Logic Input Current
VIN1 = VIN2 = 2.5V to 5.5V, VDD = 1.8V to 3.6V VIN1 = VIN2 = 2.5V to 5.5V, VDD = 1.8V to 3.6V VIL = 0V or VIH = 3.6V, EN = AGND
V V A
2
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VDD = 1.8V, TA= -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER VID0, VID1, EN Logic Input Pulldown Resistor I2C INTERFACE SDA Output Low Voltage I C Clock Frequency Bus-Free Time Between START and STOP Hold Time Repeated START Condition SCL Low Period SCL High Period Setup Time Repeated START Condition SDA Hold Time SDA Setup Time Setup Time for STOP Condition IN1 + IN2 Supply Current Minimum Output Capacitance Required for Stability OUT Voltage Range Output Overvoltage Protection tBUF tHD_STA tLOW tHIGH tSU_STA tHD_DAT tSU_DAT tSU_STO OPERATION_MODE_ = 0, VOUT = 1.27V, no switching OPERATION_MODE_ = 1, VOUT = 1.27V, fsw = 3.25MHz VOUT = 0.75V to 1.38V, IOUT = 0 to 1.8A 10mV steps Rising, 50mV hysteresis (typ) 0.750 1.65 1.8 1.3 0.6 1.3 0.6 0.6 0 0.1 0.6 0.1 0.2 0.2 0.1 -0.01 0.05 0.1 54 9 10 1.380 1.9 70
2
MAX8649
CONDITIONS Controlled by I2C command: VID0_PD = 1 VID1_PD = 1 EN_PD = 1 ISDA = 3mA
MIN
TYP
MAX
UNITS
200
320
450
k
0.03
0.4 400
V kHz s s s s s s s s A mA F V V
STEP-DOWN DC-DC REGULATOR
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3
1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VDD = 1.8V, TA= -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER CONDITIONS No load, VIN_ = 2.5V to 5.5V, VOUT = 1.27V OPERATION_MODE_ = 1 OUT Voltage Accuracy IOUT = no load, VIN_ = 2.5V to 5.5V, VOUT = 0.75V, OPERATION_MODE_ = 1 IOUT = no load, VIN_ = 2.5V to 5.5V, VOUT = 1.38V, OPERATION_MODE_ = 1 Load Regulation RL is the resistance from LX to SNS+ (output) RAMP[2:0] = 000 RAMP[2:0] = 001 RAMP[2:0] = 010 RAMP Timer RAMP[2:0] = 011 RAMP[2:0] = 100 RAMP[2:0] = 101 RAMP[2:0] = 110 RAMP[2:0] = 111 Peak Current Limit (p-Channel MOSFET) Valley Current Limit (n-Channel MOSFET) Negative Current Limit (n-Channel MOSFET) n-Channel Zero-Crossing Threshold LX pFET On-Resistance LX nFET On-Resistance LX Leakage IN2 to LX, ILX = -200mA OPERATION_MODE = 0 LX to PGND, ILX = 200mA VLX = 5.5V or 0V Internal oscillator, PWM Internal oscillator, power-save mode before entering PWM mode Operating Frequency 13MHz option 19.2MHz option 26MHz option TA = +25C TA = +85C 2.82 2.43 -1 PWM and hysteretic mode Hysteretic mode PWM mode 2.3 1.8 2.0 MIN -0.5 -1.0 -0.5 RL/25 32.50 16.25 8.125 4.063 2.031 1.016 0.508 0.254 2.8 2.4 2.5 50 0.08 0.06 0.03 0.05 3.25 3.25 fSYNC/4 fSYNC/6 fSYNC/8 3.56 4.06 MHz 3.2 3.0 3.0 0.16 0.16 0.12 +1 A A A mA A mV/s TYP MAX +0.5 +1.0 +0.5 V/A % UNITS
4
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VDD = 1.8V, TA= -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Minimum Duty Cycle Maximum Duty Cycle Minimum On- and Off-Time OUT Discharge Resistance SNS+, SNS- Input Impedance Time Delay from PWM to Power-Save Mode Time Delay from Power-Save Mode to PWM SYNCHRONIZATION (SYNC) SYNC = 00 default SYNC Capture Range SYNC Pulse Width PROTECTION CIRCUITS Thermal-Shutdown Hysteresis Thermal Shutdown 20 +160 C C SYNC = 1X default SYNC = 01 default 18.9 14.2 9.5 26.0 19.2 13.0 13 38.0 28.5 19.0 ns MHz Time required for error amplifier to stabilize before switching mode Time required for error amplifier to stabilize before switching mode During shutdown or UVLO, from SNS+ to PGND 400 CONDITIONS Forced PWM mode only, minimum duty cycle in (OPERATION_MODE_ = 1) = 0% 60 30 40 650 600 70 140 850 50 MIN TYP MAX 16 UNITS % % ns k s s
MAX8649
Note 2: All devices are 100% production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design.
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
Typical Operating Characteristics
(Typical Operating Circuit, VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VOUT = 1.1V, VDD = 1.8V, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT (0.9V OUTPUT, SYNC OFF)
MAX8649 toc01
EFFICIENCY vs. LOAD CURRENT (1.1V OUTPUT, SYNC OFF)
90 80 EFFICIENCY (%) 70 60 50 40 30 VIN = 3.2V 3.6V 4.2V POWER SAVE
MAX8649 toc02
EFFICIENCY vs. LOAD CURRENT (1.3V OUTPUT, SYNC OFF)
90 80 EFFICIENCY (%) 70 60 50 40 30 VIN = 3.2V 3.6V 4.2V POWER SAVE
MAX8649 toc03
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 FORCED PWM VIN = 3.2V 3.6V 4.2V POWER SAVE
100
100
20 10 10 0 0.0001 0.001 0.01
FORCED PWM
20 10
FORCED PWM
0.1
1
10
0 0.0001
0.001
0.01
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT (0.9V OUTPUT, 26MHz SYNC)
MAX8649 toc04
EFFICIENCY vs. LOAD CURRENT (1.1V OUTPUT, 26MHz SYNC)
MAX8649 toc05
EFFICIENCY vs. LOAD CURRENT (1.3V OUTPUT, 26MHz SYNC)
90 80 EFFICIENCY (%) 70 60 50 40 30 VIN = 3.2V 3.6V 4.2V POWER SAVE
MAX8649 toc06
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.0001 0.001 0.01 FORCED PWM VIN = 3.2V 3.6V 4.2V POWER SAVE
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 FORCED PWM VIN = 3.2V 3.6V 4.2V POWER SAVE
100
20 10 10 0 0.0001 0.001 0.01
FORCED PWM
0.1
1
10
0 0.0001
0.001
0.01
0.1
1
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
SWITCHING FREQUENCY vs. LOAD CURRENT
MAX8649 toc07
SWITCHING FREQUENCY vs. TEMPERATURE
MAX8649 toc08
NO-LOAD SUPPLY CURRENT vs. SUPPLY VOLTAGE (POWER SAVE)
MAX8649 toc09
3.5 SWITCHING FREQUENCY (MHz) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.3 0.6 0.9 1.2 1.5 POWER SAVE VIN = 3.6V VOUT = 1.3V TRANSITION TO PWM FORCED PWM
3.6 SWITCHING FREQUENCY (MHz) 3.5 3.4 3.3 3.2 3.1 3.0 NO SYNC 1.3V OUTPUT, 500mA LOAD -40 -15 10 35 60
0.6 0.5 SUPPLY CURRENT (mA) 0.4 0.3 0.2 NO SYNC 0.1 26MHz SYNC
0
85 2.5 3.5 4.5 5.5 TEMPERATURE (C) SUPPLY VOLTAGE (V)
1.8
LOAD CURRENT (A)
6
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VOUT = 1.1V, VDD = 1.8V, TA = +25C, unless otherwise noted.)
NO-LOAD SUPPLY CURRENT vs. SUPPLY VOLTAGE (FORCED PWM)
18 16 SUPPLY CURRENT (mA) 14 12 10 8 6 4 2 0 2.5 3.5 4.5 5.5 SUPPLY VOLTAGE (V) 1.26 0 0.4 0.8 1.2 1.6 2.0 LOAD CURRENT (A) 26MHz SYNC NO SYNC
MAX8649 toc10
MAX8649
OUTPUT VOLTAGE vs. LOAD CURRENT
MAX8649 toc11
OUTPUT VOLTAGE vs. LOAD CURRENT
MAX8649 toc12
20
1.32 1.31 OUTPUT VOLTAGE (V) 1.30 1.29 TA = -40C 1.28 1.27 VOUT = 1.3V POWER SAVE TA = +35C TA = +85C
1.115 1.110 OUTPUT VOLTATGE (V) 1.105 1.100 1.095 1.090 VOUT = 1.1V 1.085 0 0.3 0.6 0.9 1.2 1.5
FORCED PWM
POWER SAVE
1.8
LOAD CURRENT (A)
OUTPUT VOLTAGE vs. LOAD CURRENT
FORCED PWM 0.905 OUTPUT VOLTATGE (V) 0.900 VLX 0.895 0.890 0.885 VOUT = 0.9V 0.880 0 0.3 0.6 0.9 1.2 1.5 1.8 LOAD CURRENT (A) POWER SAVE IL
MAX8649 toc13
LIGHT LOAD SWITCHING WAVEFORMS
MAX8649 toc14
0.910
VOUT
20mV/div
2V/div
200mA/div 10mA LOAD, VOUT = 1.3V 2s/div
MEDIUM LOAD SWITCHING WAVEFORMS
MAX8649 toc15
HEAVY LOAD SWITCHING WAVEFORMS
MAX8649 toc16
VOUT
20mV/div
VOUT
20mV/div
2V/div VLX
VLX IL
2V/div
IL
500mA LOAD VOUT = 1.3V 200ns/div
500mA/div
1.8A LOAD VOUT = 1.3V 200ns/div
1A/div
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7
1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN1 = VIN2 = 3.6V, VAGND = VPGND = 0V, VOUT = 1.1V, VDD = 1.8V, TA = +25C, unless otherwise noted.)
LIGHT LOAD STARTUP WAVEFORMS
MAX8649 toc17
HEAVY LOAD STARTUP WAVEFORMS
MAX8649 toc18
10I LOAD VOUT
1V/div VOUT 100mA/div IIN
1I LOAD
1V/div
IIN
200mA/div
IL
500mA/div 5V/div IL VEN 200s/div 200s/div
500mA/div 5V/div
VEN
PREBIAS STARTUP WAVEFORMS (FORCED PWM)
MAX8649 toc19
LINE TRANSIENT RESPONSE (4.2V TO 3.2V TO 4.2V) SYNC OFF
MAX8649 toc20
VOUT
OUTPUT PREBIASED TO 1.3V STARTUP TO 1.1V 500mV/div
VIN
1V/div
VOUT IL 1A/div IL 5V/div VEN 200s/div 300mA LOAD 20s/div
20mV/div
200mA/div
LINE TRANSIENT RESPONSE (4.2V TO 3.2V TO 4.2V) 26MHz SYNC
MAX8649 toc21
LOAD TRANSIENT RESPONSE (1mA TO 1A)
MAX8649 toc22
VIN
1V/div VOUT
50mV/div
VOUT
20mV/div IL
500mA/div
IL
200mA/div 300mA LOAD 20s/div
IOUT 40s/div
1A/div
8
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
LOAD TRANSIENT RESPONSE (1A to 1mA)
MAX8649 toc23
MAX8649
LOAD TRANSIENT RESPONSE (5mA TO 1.8A)
MAX8649 toc24
50mV/div VOUT VOUT 50mV/div 1A/div
IL
500mA/div
IL
IOUT 40s/div
1A/div
IOUT 40s/div
1A/div
LOAD TRANSIENT RESPONSE (1.8A to 5mA)
MAX8649 toc25
SYNCHRONIZATION RESPONSE (26MHz SYNC)
MAX8649 toc26
FORCED PWM, NO LOAD VSYNC VOUT 100mV/div 2V/div
VOUT
20mV/div
IL
1A/div
VLX
2V/div
IOUT 1A/div 20s/div
IL 1s/div
200mA/div
OUTPUT VOLTAGE CHANGE RESPONSE
MAX8649 toc27
VVID0
10I LOAD, POWER SAVE 32mV/s RAMP 1.3V 0.9V 0.9V
2V/div
VOUT
500mV/div
IL 40s/div
200mA/div
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9
1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
Pin Description
PIN NAME FUNCTION Analog Supply Voltage Input. The input voltage range is 2.5V to 5.5V. Place an 11 resistor between IN1 and the input supply. Bypass the input supply with a 2.2F ceramic capacitor as close as possible to the 11 resistor. Bypass IN1 to the 2.2F capacitor ground plane terminal with a 0.1F ceramic capacitor as close as possible to the IC. Connect IN1 and IN2 to the same power source. Analog Ground. Connect AGND to the PCB ground plane. Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output voltage. Power-Supply Voltage Input. The input voltage range is from 2.5V to 5.5V. IN2 powers the internal p-channel and n-channel MOSFETs. Bypass IN2 to PGND with 10F and 0.1F ceramic capacitors as close as possible to the IC. Connect IN1 and IN2 to the same power source. Output Voltage Remote Sense, Positive Input. Connect SNS+ directly to the output at the load. Logic Enable Input. Drive EN high to enable the DC-DC step-down regulator, or low to place in shutdown mode. In shutdown mode, this logic input has an internal pulldown resistor to AGND. Inductor Connection. LX is connected to the drains of the internal p-channel and n-channel MOSFETs. LX is high impedance during shutdown. Output Voltage Remote Sense, Negative Input. Connect to a quiet ground directly at the load. Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output voltage. Power Ground. Connect both PGND bumps to the PCB ground plane. Logic Input Supply Voltage. Connect VDD to the logic supply driving SDA, SCL, and SYNC. Bypass VDD to AGND with a 0.1F ceramic capacitor. When VDD drops below the UVLO threshold, the I2C registers are reset, but the EN control is still active in this mode. I2C Data Input. Data is read on the rising edge of SCL and data is clocked out on the falling edge of SCL. I2C Clock Input External Clock Synchronization Input. Connect SYNC to a 13MHz, 19.2MHz, or 26MHz system clock. The DC-DC regulator can be forced to synchronize to this external clock depending on I2C setting. See Table 8. SYNC does not have an internal pulldown. Connect SYNC to AGND if not used.
A1
IN1
A2 A3
AGND VID1
A4 B1 B2 B3, B4 C1 C2 C3, C4 D1 D2 D3 D4
IN2 SNS+ EN LX SNSVID0 PGND VDD SDA SCL SYNC
10
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
SYNC
OSC
CLOCK GEN
VDD I2C INTERFACE PWM LOGIC
IN2
SCL SDA
LX
IN1 EN VID1 VID2 AGND VOLTAGE CONTROL, VREF, BIAS, ETC. VDAC
PGND
SNS+
SNS-
Figure 1. Block Diagram
Detailed Description
The MAX8649 high-efficiency, 3.25MHz step-down switching regulator delivers up to 1.8A of output current. The device operates from a 2.5V to 5.5V input voltage range, and the output voltage is I2C programmable from 0.75V to 1.38V in 10mV increments. Fully differential remote sense ensures precise DC regulation at the load. Total output error is less than 2% over load, line, and temperature.
For each of the different output modes, the following parameters are programmable: * * * Output voltage from 0.75V to 1.38V in 10mV steps Mode of operation: Forced PWM or power save Enable/disable of synchronization of switching frequency to external clock source
Dynamic Voltage Scaling
The output voltage is dynamically adjusted by use of the VID0 and VID1 logic inputs, allowing selection between four predefined operation modes/voltage configurations.
The relation between the VID0/VID1 and operation mode is given by Table 1. The VID_ inputs have internal pulldown resistors. These pulldown resistors can be disabled through the CONTROL register after the MAX8649 is enabled, achieving lowest possible quiescent current. When EN is low, the CONTROL register is reset to default, enabling the pulldown resistors (see Table 7).
Table 1. VID0 and VID1 Configuration
VID0 0 0 1 1 VID1 0 1 0 1 MODE MODE0 MODE1 MODE2 MODE3 I2C REGISTER Table 3 Table 4 Table 5 Table 6 DEFAULT SWITHCING MODE FORCED PWM POWER SAVE FORCED PWM FORCED PWM DEFAULT SYNCHRONIZATION OFF OFF OFF OFF DEFAULT OUTPUT VOLTAGE (V) 1.27 1.05 1.22 1.05
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11
1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
Enable
The MAX8649 DC-DC step-down regulator is enabled/disabled using the EN logic input. The EN input is able to handle input voltages up to VIN1, ensuring that the EN logic input can be controlled by a wide variety of signals/supplies. The EN input has an internal pulldown resistor that ensures EN is discharged during off conditions. This pulldown resistor can be disabled through the CONTROL register (see Table 7) once the MAX8649 is enabled, achieving lowest possible quiescent current. When EN is low, the CONTROL register is reset to default, enabling the pulldown resistors on EN, VID0, and VID1. See Figures 2 and 3 for detailed information on powerup and power-down sequencing and operation mode changes. done by writing to the MODE_ registers (see Table 3 to Table 6). The mode of operation can be changed at any time. In power-save mode, the MAX8649 PWM switching frequency depends on the load current. For medium to high load condition, the MAX8649 operates in fixedfrequency PWM mode. For light load conditions, the MAX8649 operates in hysteretic mode. The proprietary hysteretic PWM control scheme ensures high efficiency, fast switching, and fast transient response. This control scheme is simple: when the output voltage is below the regulation threshold, the error comparator begins a switching cycle by turning on the high-side switch. This switch remains on until the minimum ontime expires and the output voltage is above the regulation threshold plus hysteresis or the inductor current is above the current-limit threshold. Once off, the highside switch remains off until the minimum off-time expires and the output voltage falls again below the regulation threshold. During the off period, the lowside synchronous rectifier turns on and remains on until either the high-side switch turns on again or the inductor current approaches zero. The internal synchronous rectifier eliminates the need for an external Schottky diode.
DC-DC Regulator Operating Modes
The MAX8649 operates in one of four modes determined by the state of the VID_ inputs (see Table 1). At power-up, the MAX8649 is default set to operate in power-save operation for MODE1 and forced-PWM mode for MODE0, MODE2, and MODE3. For each of the operation modes, MODE0 to MODE3, the MAX8649 DC-DC step-down regulator can be set to operate in either power-save mode or forced-PWM mode. This is
A IN 1.27V OUT B
C
D
E
1.22V
1.05V
EN
VID0
VID1
VDD
A: POWER CONNECTED TO IN1 AND IN2. B: EN LOGIC INPUT PULLED HIGH, OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE DEFAULT VALUE OF THE I2C REGISTER FOR MODE0 (SEE TABLE 1). C: OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE I2C REGISTER FOR MODE1. D: OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE DEFAULT VALUE OF I2C REGISTER FOR MODE3. E: VDD PULLED HIGH, ENABLING I2C INTERFACE.
Figure 2. Power-Up Sequence
12 ______________________________________________________________________________________
1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
A IN B
OUT
EN
VDD A: VDD PULLED LOW, I2C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1) AND THE OUTPUT VOLTAGE CHANGES TO THE DEFAULT VALUE. B: EN LOGIC INPUT PULLED LOW, STEP-DOWN REGULATOR ENTERS SHUTDOWN MODE.
Figure 3a. Shutdown by Pulling VDD Low Before EN
A B
IN
OUT
EN
VDD A: EN LOGIC INPUT PULLED LOW, STEP-DOWN REGULATOR ENTERS I2C READY MODE, OUTPUT DISABLED. B: VDD PULLED LOW, I2C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1).
Figure 3b. Shutdown by Pulling EN Low Before VDD
A
IN1
OUT
EN
VDD
A: IN1 DROPS BELOW UVLO, IC ENTERS SHUTDOWN MODE, I2C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1).
Figure 3c. Shutdown Due to IN1 Undervoltage Lockout
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP
The transition between PWM and hysteretic operation is based on the number of consecutive zero-crossing cycles. When more than 16 consecutive zero-crossing cycles are detected, the DC-DC step-down converter enables the bias for hysteretic operation. Once correctly biased and the number of consecutive zero-crossing cycles exceeds 24, the DC-DC step-down converter begins hysteretic operation. During hysteretic operation, there is a silent DC offset due to the use of valley regulation. See Figure 4. When operating in power-save mode and the load current is increased so that the number of consecutive zero-crossing cycles is less than 16, the PWM mode is biased. Once fully biased and the number of zerocrossing cycles drops below 8, the DC-DC converter then begins PWM operation. Since there is a delay between the increase in load current and the DC-DC converter starting PWM, the converter supports full current on the output during hysteretic operation. See Figure 5 for a detailed state diagram. Power-save operation offers improved efficiency at light loads by changing to hysteretic mode, reducing the switching frequency depending on the load condition. With moderate to heavy loading, the regulator switches at a fixed switching frequency as it does in forced-PWM mode. In power-save mode, the transition from hysteretic mode to fixed-frequency switching occurs at the load current specified in the following equation: V -V VOUT IOUT = IN OUT x 2xL VIN x fOSC In forced-PWM mode, the regulator operates with a constant (3.25MHz or synchronized to external clock source) switching frequency regardless of output load. Forced-PWM mode is ideal for low-noise systems because switching harmonics occur at multiples of the constant switching frequency and are easily filtered. However, light-load power consumption in forced-PWM mode is higher than that of power-save mode.
MAX8649
REGULATION THRESHOLD
OUTPUT RIPPLE
Figure 4. Output Regulation in Hysteretic Operation
MORE THAN 16 CONSECUTIVE ZERO-CROSSING CYCLES
PWM MODE
PWM MODE WITH POWER-SAVE MODE BIASED
POWER SAVE NOT READY
LESS THAN 8 CONSECUTIVE ZERO-CROSSING CYCLES
LESS THAN 8 CONSECUTIVE ZERO-CROSSING CYCLES AND PWM MODE READY
MORE THAN 24 CONSECUTIVE ZERO-CROSSING CYCLES AND POWER-SAVE MODE READY
MORE THAN 24 CONSECUTIVE ZERO-CROSSING CYCLES
PWM NOT READY
POWER-SAVE MODE WITH PWM BIASED
POWER-SAVE MODE
LESS THAN 16 CONSECUTIVE ZERO-CROSSING CYCLES
Figure 5. Mode Change for DC-DC Step-Down Converter
14 ______________________________________________________________________________________
1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP
Soft-Start
The MAX8649 includes internal soft-start circuitry that eliminates inrush current at startup, reducing transients on the input source (see the Typical Operating Characteristics). Soft-start is particularly useful for high-impedance input sources, such as Li+ and alkaline cells. When enabling the MAX8649 into a prebiased output, the MAX8649 performs a complete soft-start cycle. behavior in power-save mode. When the regulator is set for power-save mode and the RAMP_DOWN bit is cleared, the ramp-down is not actively controlled, and the regulator output voltage ramps down at the rate determined by the output capacitance and the external load. Small loads result in an output-voltage decay that is slower than that specified by RAMP; large loads result in an output-voltage decay that is no faster than that specified by RAMP When the RAMP_DOWN bit is set in power-save mode, the zero-cross comparator is disabled during the ramp-down condition. Active rampdown functionality is inherent in forced-PWM operation. Calculate the maximum and minimum values for the ramp rate as follows: V 1 tRAMP _ MIN = OUT _ LSB x RAMP _ CODE tCLK _ MAX 2 V 1 tRAMP _ MAX = OUT _ LSB x tCLK _ MIN 2RAMP _ CODE where: VOUT _ LSB = 10mV tCLK _ MAX = tCLK _ MIN = 1 fSW _ MIN 1 fSW _ MAX
MAX8649
Synchronous Rectification
An internal n-channel synchronous rectifier eliminates the need for an external Schottky diode and improves efficiency. The synchronous rectifier turns on during the second half of each switching cycle (off-time). During this time, the voltage across the inductor is reversed, and the inductor current ramps down. In PWM mode, the synchronous rectifier turns off at the end of the switching cycle. In power-save mode, the synchronous rectifier turns off when the inductor current falls below 50mA (typ) or at the end of the switching cycle, whichever occurs first.
Ramp-Rate Control
The MAX8649 output voltage has an actively controlled variable ramp rate, set with the I 2 C interface (see Figures 6, 7, and 8). The value set in the RAMP register controls the output voltage ramp rate. The RAMP_DOWN bit controls the active ramp-down
OUTPUT VOLTAGE DELTA V = 10mV VOUT2
fSW = 3.25MHz 10% for PWM operation fSW = 3.25MHz 25% for hysteretic operation f fSW = SYNC n
10mV/RAMP RATE
VOUT1 TIME
fSYNC = frequency of external clock n = 4 for 13MHz, 6 for 19.2MHz, and 8 for 26MHz RAMP_CODE = value of the RAMP[2:0] register (see Table 9)
FINAL OUTPUT VOLTAGE
Figure 6. Ramp-Up Function
OUTPUT VOLTAGE VOUT2
DELTA V = 10mV VOUT1
10mV/RAMP RATE TIME
MODE CHANGE TO HIGHER VOUT
MODE CHANGE TO LOWER VOUT
Figure 7. Ramp-Down Function
Figure 8. Mode Change Before Final Value is Reached
15
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
SDA
SCL
DATA LINE STABLE DATA VALID
CHANGE OF DATA ALLOWED
Figure 9. I2C Bit Transfer
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the MAX8649. When internal thermal sensors detect a die temperature in excess of +160C (typ), the DC-DC step-down regulator is shut down, allowing the IC to cool. The DC-DC step-down regulator is turned on again after the junction cools by 20C (typ), resulting in a pulsed output during continuous thermal-overload conditions. During thermal overload, the I 2 C interface remains active and all register values are maintained.
Each transmit sequence is framed by a START (S) condition and a STOP (P) condition. Each data packet is 9 bits long; 8 bits of data followed by the acknowledge bit. The MAX8649 supports data transfer rates with SCL frequencies up to 400kHz.
I2C Interface An I2C-compatible, 2-wire serial interface controls the step-down converter output voltage, ramp rate, operating mode, and synchronization. The serial bus consists of a bidirectional serial-data line (SDA) and a serialclock input (SCL). The master initiates data transfer on the bus and generates SCL to permit data transfer.
I2C is an open-drain bus. SDA and SCL require pullup resistors (500 or greater). Optional (24) in series with SDA and SCL protect the device inputs from highvoltage spikes on the bus lines. Series resistors also minimize crosstalk and undershoot on bus signals.
START and STOP Conditions When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START (S) condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP (P) condition is a low-to-high transition on SDA, while SCL is high (Figure 10).
SDA
SCL
Bit Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse (see Figure 9). Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section for more information).
START CONDITION
STOP CONDITION
Figure 10. I2C START and STOP Conditions
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
SDA SCL
MASTER TRANSMITTER/RECEIVER
SLAVE RECEIVER
SLAVE TRANSMITTER/RECEIVER
Figure 11. I2CMaster/Slave Configuration
A START condition from the master signals the beginning of a transmission to the MAX8649. The master terminates transmission by issuing a not acknowledge followed by a STOP condition (see the Acknowledge section for more information). The STOP condition frees the bus. To issue a series of commands to the slave, the master can issue REPEATED START (Sr) commands instead of a STOP command to maintain control of the bus. In general, a REPEATED START command is functionally equivalent to a regular START command. When a STOP condition or incorrect address is detected, the MAX8649 internally disconnects SCL from the serial interface until the next START condition, minimizing digital noise and feedthrough.
SDA OUTPUT FROM TRANSMITTER
D7
D6
D0
NOT ACKNOWLEDGE SDA OUTPUT FROM RECEIVER
SCL FROM MASTER
ACKNOWLEDGE 1 2 8 9
START CONDITION
CLOCK PULSE FOR ACKNOWLEDGEMENT
System Configuration A device on the I2C bus that generates a message is called a transmitter and a device that receives the message is a receiver. The device that controls the message is the master and the devices that are controlled by the master are called slaves. See Figure 11. Acknowledge The number of data bytes between the START and STOP conditions for the transmitter and receiver are unlimited. Each 8-bit byte is followed by an acknowledge bit. The acknowledge bit is a high-level signal put on SDA by the transmitter during which time the master generates an extra acknowledge-related clock pulse. A slave receiver that is addressed must generate an acknowledge after each byte it receives. Also, a master receiver must generate an acknowledge after each byte it receives that has been clocked out of the slave transmitter. See Figure 12.
Figure 12. I2C Acknowledge
The device that acknowledges must pull down the DATA line during the acknowledge clock pulse, so that the DATA line is stable low during the high period of the acknowledge clock pulse (setup and hold times must also be met). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave SDA high to enable the master to generate a STOP (P) condition.
Register Reset The I2C resisters reset back to their default values when the voltage at either IN1 or V DD drops below the corresponding UVLO threshold (see the Electrical Characteristics table).
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17
1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
A OUT SDA VID0 VID1 VDD A: I2C START COMMAND. B: I2C SLAVE ADDRESS OF MAX8649 SEND OUT. C: MAX8649 I2C REGISTER POINTER SEND OUT. D: MAX8649 DATA SEND OUT. E: MAX8649 ISSUES ACKNOWLEDGE AND CHANGES THE OUTPUT VOLTAGE ACCORDING TO NEW I2C SETTINGS. S SLAVE ID ASr REG PTR ASr DATA A P B C D E
Figure 13. Update Output Operation
Update of Output Operation Mode If updating the output voltage or Operation Mode register for the mode that the MAX8649 is currently operating in, the output voltage/operation mode is updated at the same time the MAX8649 sends the acknowledge for the I2C data byte (see Figure 13). Slave Address A bus master initiates communication with a slave device (MAX8649) by issuing a START (S) condition followed by the slave address. The slave address byte consists of 7 address bits (1100 000x) and a read/write bit (R/W). After receiving the proper address, the MAX8649 issues an acknowledge by pulling SDA low during the ninth clock cycle. Other slave addresses can be assigned. Contact the factory for details. Write Operations The MAX8649 recognizes the write byte protocol as defined in the SMBus specification and shown in Figures 14a and 14b. The write byte protocol allows the I2C master device to send 1 byte of data to the slave device. The write byte protocol requires a register pointer address for the subsequent write. The MAX8649 acknowledges any register pointer even though only a subset of those registers actually exists in the device. The write byte protocol is as follows: 1) The master sends a start command. 2) The master sends the 7-bit slave address followed by a write bit. 3) The addressed slave asserts an acknowledge by pulling SDA low.
18
4) The master sends an 8-bit register pointer. 5) 6) 7) 8) The slave acknowledges the register pointer. The master sends a data byte. The slave acknowledges the data byte. The slave updates with the new data.
9) The master sends a STOP (P) condition. In addition to the write-byte protocol, the MAX8649 can write to multiple registers as shown in Figure 14b. This protocol allows the I2C master device to address the slave only once and then send data to a sequential block of registers starting at the specified register pointer. Use the following procedure to write to a sequential block of registers: 1) The master sends a start command. 2) The master sends the 7-bit slave address followed by a write bit. 3) The addressed slave asserts an acknowledge by pulling SDA low. 4) The master sends the 8-bit register pointer of the first register to write. 5) 6) 7) 8) 9) The slave acknowledges the register pointer. The master sends a data byte. The slave acknowledges the data byte. The slave updates with the new data. Steps 6 to 8 are repeated for as many registers in the block, with the register pointer automatically incremented each time. 10) The master sends a STOP condition.
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
LEGEND MASTER TO SLAVE SLAVE TO MASTER a) WRITING TO A SINGLE REGISTER WITH THE WRITE BYTE PROTOCOL 1 S 7 SLAVE ADDRESS R/W b) WRITING TO MULTIPLE REGISTERS 1 S 7 SLAVE ADDRESS R/W ... 1 0 1 A 8 REGISTER POINTER X 8 DATA X+n-1 1 A 1 A 8 DATA X 8 DATA X+n 1 A 1 AP 8 DATA X+1 NUMBER OF BITS 1 A ... NUMBER OF BITS 1 0 1 A 8 REGISTER POINTER 1 A 8 DATA 1 A 1 P NUMBER OF BITS
Figures 14a and 14b. Writing to the MAX8649
Read Operations The method for reading a single register (byte) is shown in Figure 15a. To read a single register: 1) The master sends a start command.
2) The master sends the 7-bit slave address followed by a write bit. 3) The addressed slave asserts an acknowledge by pulling SDA low. 4) The master sends an 8-bit register pointer. 5) The slave acknowledges the register pointer. 6) The master sends a repeated START (S) condition. 7) The master sends the 7-bit slave address followed by a read bit. 8) The slave asserts an acknowledge by pulling SDA low. 9) The slave sends the 8-bit data (contents of the register). 10) The master asserts a not acknowledge by keeping SDA high. 11) The master sends a STOP (P) condition. In addition, the MAX8649 can read a block of multiple sequential registers as shown in Figure 15b. Use the following procedure to read a sequential block of registers:
1) The master sends a start command. 2) The master sends the 7-bit slave address followed by a write bit. 3) The addressed slave asserts an acknowledge by pulling SDA low. 4) The master sends an 8-bit register pointer of the first register in the block. 5) The slave acknowledges the register pointer. 6) The master sends a repeated START condition. 7) The master sends the 7-bit slave address followed by a read bit. 8) The slave asserts an acknowledge by pulling SDA low. 9) The slave sends the 8-bit data (contents of the register). 10) The master asserts an acknowledge by pulling SDA low when there is more data to read, or a not acknowledge by keeping SDA high when all data has been read. 11) Steps 9 and 10 are repeated for as many registers in the block, with the register pointer automatically incremented each time. 12) The master sends a STOP condition.
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
LEGEND MASTER TO SLAVE SLAVE TO MASTER
a) READING A SINGLE REGISTER 1 S 7 SLAVE ADDRESS R/W b) READING MULTIPLE REGISTERS 1 S 7 SLAVE ADDRESS R/W 8 ... DATA X+1 1 A ... 8 DATA X+n-1 1 0 1 A 8 REGISTER POINTER X 1 A 1 Sr 7 SLAVE ADDRESS R/W 1 A 11 1 A 8 DATA X 1 A ... NUMBER OF BITS 1 0 1 A 8 REGISTER POINTER 1 1 7 SLAVE ADDRESS R/W 1 1 1 A 8 DATA 1 A 1 P NUMBER OF BITS
A Sr
8 DATA X+n
1
1
NUMBER OF BITS
AP
Figures 15a and 15b. Reading from the MAX8649
SDA tSU_STA tHD_DAT tHIGH tBUF tHD_STA tSU_STO
tLOW
tSU_DAT
SCL tHD_STA tR START CONDITION
tF REPEATED START CONDITION STOP CONDITION START CONDITION
Figure 16. I2C Timing Diagram
20
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP
Table 2. I2C Register Map
POINTER 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x08 0x09 REGISTER MODE0 MODE1 MODE2 MODE3 CONTROL SYNC RAMP CHIP_ID1 CHIP_ID2 POR 0xB4 0x1E 0xB0 0x9E 0xE0 0x00 0x01 0x20 0x0D BIT7 OPER MODE OPER MODE OPER MODE OPER MODE EN_PD BIT6 SYNC MODE SYNC MODE SYNC MODE SYNC MODE VID0_PD RAMP[2:0] DIE TYPE[7:4] DASH[3:0] VID1_PD -- -- -- BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 OUT MODE0[5:0] OUT MODE1[5:0] OUT MODE2[5:0] OUT MODE3[5:0] -- -- -- -- -- -- -- RAMP_DOWN -- -- --
MAX8649
SYNC[1:0]
FORCE_HYS FORCE_OSC
DIE TYPE[3:0] MASK REV[3:0]
Table 3. I2C Register: MODE0
This register contains output voltage and operation mode control for MODE0, VID0 = GND, VID1 = GND.
REGISTER NAME Address Reset Value Type Special Features MODE0 0x00h 0xB4h Read/write Reset upon VDD or IN1 UVLO
BIT
NAME
DESCRIPTION DC-DC Step-Down Converter Operation Mode for MODE0 0 = DC-DC converter automatically changes between hysteretic mode for light load conditions and PWM mode for medium to heavy load conditions. 1 = DC-DC converter operates in forced-PWM mode. Disable/Enable Synchronization to External Clock 0 = DC-DC converter ignores the external SYNC input regardless of operation mode. 1 = DC-DC converter synchronizes to external SYNC input when available. Output Voltage Selection for MODE0 000000 = 0.75V 000001 = 0.76V 110011 = 1.26V 110100 = 1.27V 110101 = 1.28V 111110 = 1.37V 111111 = 1.38V
DEFAULT VALUE
B7 (MSB)
OPERATION_MODE0
1
B6
SYNC_MODE0
0
B5 B4 B3 B2 B1 B0 (LSB) OUT_ MODE0 [5:0]
110100
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
Table 4. I2C Register: MODE1
This register contains output voltage and operation mode control for MODE1, VID1 = GND, VID0 = VDD.
REGISTER NAME Address Reset Value Type Special Features MODE1 0x01h 0x1Eh Read/write Reset upon VDD or IN1 UVLO
BIT
NAME
DESCRIPTION DC-DC Step-Down Converter Operation Mode for MODE1 0 = DC-DC converter automatically changes between hysteretic mode for light load conditions and PWM mode for medium to heavy load conditions. 1 = DC-DC converter operates in forced-PWM mode. Disable/Enable Synchronization to External Clock 0 = DC-DC converter ignores the external SYNC input regardless of operation mode. 1 = DC-DC converter synchronizes to external SYNC input when available. Output Voltage Selection for MODE1 000000 = 0.75V 000001 = 0.76V 011101 = 1.04V 011110 = 1.05V 011111 = 1.06V 111110 = 1.37V 111111 = 1.38V
DEFAULT VALUE
B7 (MSB)
OPERATION_MODE1
0
B6
SYNC_MODE1
0
B5 B4 B3 B2 B1 B0 (LSB) OUT_MODE1[5:0]
011110
22
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP
Table 5. I2C Register: MODE2
This register contains output voltage and operation mode control for MODE2, VID1 = VDD, VID0 = GND.
REGISTER NAME Address Reset Value Type Special Features MODE2 0x02h 0xB0h Read/write Reset upon VDD or IN1 UVLO
MAX8649
DEFAULT VALUE
BIT
NAME
DESCRIPTION DC-DC Step-Down Converter Operation Mode for MODE2 0 = DC-DC converter automatically changes between hysteretic mode for light load conditions and PWM mode for medium to heavy load conditions. 1 = DC-DC converter operates in forced-PWM mode. Disable/Enable Synchronization to External Clock 0 = DC-DC converter ignores the external SYNC input regardless of operation mode. 1 = DC-DC converter synchronizes to external SYNC input when available. Output Voltage Selection for MODE2 000000 = 0.75V 000001 = 0.76V 101110 = 1.21V 101111 = 1.22V 110000 = 1.23V 111110 = 1.37V 111111 = 1.38V
B7 (MSB)
OPERATION_MODE2
1
B6
SYNC_MODE2
0
B5 B4 B3 B2 B1 B0 (LSB) OUT_MODE2[5:0]
110000
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
Table 6. I2C Register: MODE3
This register contains output voltage and operation mode control for MODE3, VID1 = VDD, VID0 = VDD.
REGISTER NAME Address Reset Value Type Special Features MODE3 0x03h 0x9Eh Read/write Reset upon VDD or IN1 UVLO
BIT
NAME
DESCRIPTION DC-DC Step-Down Converter Operation Mode for MODE3 0 = DC-DC converter automatically changes between hysteretic mode for light load conditions and PWM mode for medium to heavy load conditions. 1 = DC-DC converter operates in forced-PWM mode. Disable/Enable Synchronization to External Clock 0 = DC-DC converter ignores the external SYNC input regardless of operation mode. 1 = DC-DC converter synchronizes to external SYNC input when available. Output Voltage Selection for MODE3 000000 = 0.75V 000001 = 0.76V 011101 = 1.04V 011110 = 1.05V 011111 = 1.06V 111110 = 1.37V 111111 = 1.38V
DEFAULT VALUE
B7 (MSB)
OPERATION_MODE3
1
B6
SYNC_MODE3
0
B5 B4 B3 B2 B1 B0 (LSB) OUT_MODE3[5:0]
011110
24
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP
Table 7. I2C Register: CONTROL
This register enables or disables pulldown resistors.
REGISTER NAME Address Reset Value Type Special Features CONTROL 0x04h 0xE0h Read/write Reset upon VDD, IN1 UVLO or EN pulled low
MAX8649
BIT B7 (MSB) B6 B5 B4 B3 B2 B1 B0 (LSB)
NAME EN_PD VID0_PD VID1_PD -- -- -- -- --
DESCRIPTION 0 = Pulldown on EN input is disabled. 1 = Pulldown on EN input is enabled. 0 = Pulldown on VID0 input is disabled. 1 = Pulldown on VID0 input is enabled. 0 = Pulldown on VID1 input is disabled. 1 = Pulldown on VID1 input is enabled. Reserved for future use. Reserved for future use. Reserved for future use. Reserved for future use. Reserved for future use.
DEFAULT VALUE 1 1 1 0 0 0 0 0
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
Table 8. I2C Register: SYNC
This register specifies the clock frequency of external clock source.
REGISTER NAME Address Reset Value Type Special Features SYNC 0x05h 0x00h Read Reset upon VDD or IN1 UVLO
BIT B7 (MSB)
NAME
DESCRIPTION Sets Clock Frequency of External Clock Present on SYNC Input 00 = 26MHz 01 = 13MHz 10 = 19.2MHz 11 = 19.2MHz Reserved for future use. Reserved for future use. Reserved for future use. Reserved for future use. Reserved for future use. Reserved for future use.
DEFAULT VALUE
SYNC[1:0] B6 B5 B4 B3 B2 B1 B0 (LSB) -- -- -- -- -- --
00
0 0 0 0 0 0
26
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP
Table 9. I2C Register: RAMP
This register controls of ramp-up/down function.
REGISTER NAME Address Reset Value Type Special Features RAMP 0x06h 0x01h Read Reset upon VDD or IN1 UVLO
MAX8649
DEFAULT VALUE
BIT
NAME Control the RAMP Timing 000 = 32mV/s 001 = 16mV/s 010 = 8mV/s 011 = 4mV/s 100 = 2mV/s 101 = 1mV/s 110 = 0.5mV/s 111 = 0.25mV/s
DESCRIPTION
B7 (MSB)
B6
RAMP[2:0]
000
B5
B4
FORCE_HYS
Only Valid When Converter is Operating in OPERATION_MODE 0 0 = Automatically change between power-save mode and PWM mode, depending on load current. 1 = Converter always operates in power-save mode regardless of load current as long as OPERATION_MODE = 0. If OPERATION_MODE = 1, this setting is ignored. Force Oscillator While Running in Hysteretic Mode 0 = Internal oscillator is disabled in power save when operating in hysteretic mode. 1 = Internal oscillator is enabled in power save even when operating in hysteretic mode. Reserved for future use. Active Ramp-Down Control for Power-Save Mode 0 = Active ramp disabled for power-save mode. 1 = During ramp-down, the error crossing detector is disabled allowing negative current to flow thought the nMOS device. Reserve for future use.
0
B3
FORCE_OSC
0
B2
--
0
B1
RAMP_DOWN
0
B0 (LSB)
--
1
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
Table 10. I2C Register: CHIP_ID1
This register contains the die type number (20).
REGISTER NAME Address Reset Value Type Special Features CHIP_ID1 0x08h 0x20h Read --
BIT B7 (MSB) B6 B5 B4 B3 B2 B1 B0 (LSB)
NAME
DESCRIPTION
DEFAULT VALUE
DIE_TYPE[7:4]
BCD character (2)
0010
DIE_TYPE[3:0]
BCD character (0)
0000
Table 11. I2C Register: CHIP_ID2
This register contains the die type dash number and mask revision level.
REGISTER NAME Address Reset Value Type Special Features CHIP_ID2 0x09h 0x0Ah Read --
BIT B7 (MSB) B6 B5 B4 B3 B2 B1 B0 (LSB)
NAME
DESCRIPTION
DEFAULT VALUE
DASH
BCD character 0
0000
MASK_REV
BCD character A
1010
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP
Applications Information
Inductor Selection
Calculate the inductor value (LIDEAL) using the following formula: LIDEAL = 4 x VIN x D x (1- D) IOUT(MAX ) x fOSC Given LIDEAL, the peak-to-peak inductor ripple current is 0.25 x IOUT(MAX). The peak inductor current is 1.125 x IOUT(MAX). Make sure that the saturation current of the inductor exceeds the peak inductor current, and the rated maximum DC inductor current exceeds the maximum output current (OUT(MAX)). Inductance values smaller than LIDEAL can be used to reduce inductor size; however, if much smaller values are used, peak inductor current rises and a larger output capacitance may be required to suppress output ripple. Larger inductance values than LIDEAL can be used to obtain higher output current, but typically require a physically larger inductor size. See Table 12 for recommended inductors.
MAX8649
This sets the peak-to-peak inductor current ripple to 1/4 the maximum output current. The oscillator frequency, fOSC, is 3.25MHz, and the duty cycle, D, is: V D = OUT VIN
Table 12. Recommended Inductors
MANUFACTURER SERIES KSLI-2520AG Multilayer Hitachi Metals KLSI-2016AG INDUCTANCE (H) 1.0 1.5 2.2 0.75 1.0 1.5 0.5 1.3 1.6 2.0 1.0 1.5 2.2 1.0 1.5 1.0 2.2 0.56 1.2 1.5 2.0 0.56 0.80 1.0 1.5 2.2 0.68 1.0 1.5 1.8 2.2 DC RESISTANCE ( typ) 0.075 0.075 0.115 0.09 0.09 0.13 0.11 0.10 0.09 0.06 0.11 0.13 0.14 0.03 0.04 0.048 0.070 0.032 0.044 0.050 0.067 0.072 0.092 0.125 0.134 0.070 0.080 0.085 0.120 0.150 CURRENT RATING (mA) 1800 1800 1400 1500 1500 1100 2000 2000 2000 2000 1100 1000 900 2100 1800 2000 1400 2300 1800 1500 1400 1800 1600 1400 1150 2300 1800 1600 1300 1200 DIMENSIONS L x W x H (mm) 2.5 x 2.0 x 1.0
2.0 x 1.6 x 1.0
FDK
MIPSA2520D Multilayer
2.5 x 2.0 x 0.5
CKP3216 Multilayer Taiyo Yuden NR3015 TDK VLS3015T
3.2 x 1.6 x 0.9
3.0 x 3.0 x 1.5 3.0 x 3.0 x 1.5
TOKO
DE2812C
3.2 x 3.0 x 1.2
LPS3008
3.0 x 3.0 x 0.8
Coilcraft
LPS3010
3.0 x 3.0 x 1.0
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP MAX8649
Input Capacitor Selection
The input capacitor in a step-down DC-DC regulator reduces current peaks drawn from the battery or other input power source and reduces switching noise in the controller. A 10F ceramic capacitor in parallel with a 0.1F ceramic capacitor is recommended for most applications. The impedance of the input capacitor at the switching frequency should be less than that of the input source so that high-frequency switching currents do not pass through the input source. The input capacitor must meet the input ripple-current requirement imposed by the step-down regulator. Ceramic capacitors are preferred due to their resilience to power-up surge currents. Choose the input capacitor so that the temperature rises due to input ripple current do not exceed approximately +10C. For a step-down DC-DC regulator, the maximum input ripple current is 1/2 of the output. This maximum input ripple current occurs when the step-down regulator operates at 50% duty factor (VIN = 2 x VOUT). Refer to the MAX8649 Evaluation Kit data sheet for specific input capacitor recommendations. Additional ripple due to capacitor ESR is: VRIPPLE (ESR) = IL (PEAK) x ESR Refer to the MAX8649 Evaluation Kit data sheet for specific output capacitor recommendations.
Power Dissipation
The MAX8649 has a thermal-shutdown feature that protects the IC from damage when the die temperature exceeds +160C. See the Thermal-Overload Protection section for more information. To prevent thermal overload and allow the maximum load current on each regulator, it is important to ensure that the heat generated by the MAX8649 can be dissipated into the PCB. When properly mounted on a multilayer PCB, the junction-to-ambient thermal resistance ( JA ) is typically 76C/W.
PCB Layout
Due to fast switching waveforms and high current paths, careful PCB layout is required to achieve optimal performance. Minimize trace lengths between the IC and the inductor, the input capacitor, and the output capacitor; keep these traces short, direct, and wide. The ground connections of CIN and COUT should be as close together as possible and connected to PGND. Connect AGND and PGND directly to the ground plane. The MAX8649 evaluation kit illustrates an example PCB layout and routing scheme.
Output Capacitor Selection
The step-down DC-DC regulator output capacitor keeps output ripple small and ensures control-loop stability. A 10F ceramic capacitor in parallel with a 0.1F ceramic capacitor is recommended for most applications. The output capacitor must also have low impedance at the switching frequency. Ceramic, polymer, and tantalum capacitors are suitable, with ceramic exhibiting the lowest ESR and lowest high-frequency impedance. Output ripple due to capacitance (neglecting ESR) is approximately: VRIPPLE = IL (PEAK) 2 x fOSC x COUT
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1.8A Step-Down Regulator with Differential Remote Sense in 2mm x 2mm WLP
Chip Information
PROCESS: BiCMOS
PACKAGE TYPE 16 WLP 0.5mm Pitch
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE CODE W162B2+1 DOCUMENT NO. 21-0200
MAX8649
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